Principal Silicon Design Methodology Engineer

Microsoft · ✓ Verified company
📍 India, Telangana, Hyderabad · On-site · Full-time

About the role

Own one or more libraries' design/qualification end to end — specification, RTL/behavioral modeling, verification, static qualifications and release — you're expected to be accountable for the library IP's design quality across all consuming silicon projects. Drive front-end qualification of library IPs through Lint, CDC, RDC, synthesis and low-power checks, and drive them to clean, reproducible, multi-project releases for concurrent silicon programs. Build and maintain qualification and regression pipelines for library, triage failures, root cause and drive them to closure. Act as the front-line technical owner for partner-reported issues against library IP: root cause failures and integration issues in partner environments, reproduce against standalone libraries, and deliver fixes with a predictable turnaround. Partner with SoC design, DV, methodology, physical design and EDA vendor teams to align library behavior, qualification criteria and release readiness; drive resolution of cross-team technical issues. Provide functional leadership to a team of front-end CAD engineers: set technical direction, review designs and PRs, mentor engineers, and improve backlog, sprint and release hygiene. Communicate status, risk and release readiness clearly to engineering leadership and partner stakeholders across time zones and demonstrate growth mindset. BS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience. At least 6 years of experience in front-end digital design and development. At least 2 years of experience taking IP through front-end qualification—including lint, clock-domain crossing (CDC), reset-domain crossing (RDC), synthesis, and low-power checks—and release. Understanding of standard cells mapping, memories, and behavioral design modeling. Ability to analyze the functionality and connectivity of existing IP and implement incremental design improvements. Hands-on experience with IP design simulation and debugging workflows. MS in Electrical Engineering, Computer Engineering, Computer Science or equivalent work experience. 6+ years of relevant experience. End-to-end ownership of shared design/verification libraries and multi-project consumption. Knowledge of the front-end VLSI design lifecycle, with demonstrated contributions to design methodology improvements. Experience developing and maintaining CI/CD pipelines for design and verification workflows. Experience applying AI-assisted techniques to improve design and verification of productivity. Demonstrated technical leadership and mentoring skills. This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. *