Physical Design and Implementation Engineer, GPU

Google · ✓ Verified company
📍 Bengaluru, Karnataka, India · On-site · Full-time

About the role

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. - Use analytical and simulation techniques to ensure Performance, Power, and Area (PPA) is within defined requirements and develop all aspects of ASIC RTL2GDS implementation for high PPA designs. - Collaborate with cross-functional teams to debug failures or performance shortfalls program goals in lab or simulation. - Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area. - Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts. - Manage block and full-chip level physical implementation and QoR (power, timing, area). Minimum qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. - 8 years of experience in physical design and participation in 4 chip tape outs. Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. - Experience with scripting languages such as Perl, Python, or TCL. - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. - 8 years of experience in physical design and participation in 4 chip tape outs.