Project Role : Functional Verification Engineer

Project Role Description : Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.

Must have skills : SoC Verification

Good to have skills : NA

Minimum 5 year(s) of experience is required

Educational Qualification : 15 years full time education

Summary:

As a Functional Verification Engineer, a typical day involves designing and implementing comprehensive testbenches to validate the functional accuracy of digital designs at both block and system levels. The role requires creating various types of tests, including constrained-random, directed, and coverage-driven, to thoroughly assess the design's behavior. Collaboration with design and architecture teams is essential to uncover edge cases and guarantee exhaustive functional coverage prior to tape-out. This position demands a proactive approach to problem-solving and continuous communication across multiple teams to ensure the highest quality of verification outcomes.

Roles & Responsibilities:

- Expected to be an SME, collaborate and manage the team to perform.

- Responsible for team decisions.

- Engage with multiple teams and contribute on key decisions.

- Provide solutions to problems for their immediate team and across multiple teams.

- Lead the development and review of verification plans to ensure alignment with project goals.

- Mentor junior team members to enhance their technical skills and understanding of verification methodologies.

- Coordinate with cross-functional teams to integrate verification efforts and resolve design issues efficiently.

Professional & Technical Skills:

- Must To Have Skills: Proficiency in SoC Verification.

- Strong knowledge of verification methodologies including constrained-random testing and coverage-driven verification.

- Experience with SystemVerilog and Universal Verification Methodology for testbench development.

- Ability to analyze complex digital designs and identify potential corner cases.

- Familiarity with simulation tools and debugging techniques to ensure thorough verification.

- Capability to collaborate effectively with design and architecture teams to enhance verification quality.

Additional Information:

- The candidate should have minimum 5 years of experience in SoC Verification.

- This position is based at our BDC6F - SEZ office.

- A 15 years full time education is required.

15 years full time education

About Accenture

Accenture is a leading global professional services company that helps the world’s leading businesses, governments and other organizations build their digital core, optimize their operations, accelerate revenue growth and enhance citizen services—creating tangible value at speed and scale. We are a talent- and innovation-led company with approximately 791,000 people serving clients in more than 120 countries. Technology is at the core of change today, and we are one of the world’s leaders in helping drive that change, with strong ecosystem relationships. We combine our strength in technology and leadership in cloud, data and AI with unmatched industry experience, functional expertise and global delivery capability. Our broad range of services, solutions and assets across Strategy & Consulting, Technology, Operations, Industry X and Song, together with our culture of shared success and commitment to creating 360° value, enable us to help our clients reinvent and build trusted, lasting relationships. We measure our success by the 360° value we create for our clients, each other, our shareholders, partners and communities.Visit us at www.accenture.com 

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